Module not defined model sim tutorial

Re: Simulate COREGEN in ModelSim thanks for your help~ i remove the test_core.xco file, and add test_core.v into my project. but it need some *.v files. i found them in the ipcore_dir est_coresrc folder. but i can't find a file which defined a module called "test_core_gtp_wrapper". Modelsim Tutorial ECGR2181 Introduction: Modelsim is a software application that is used for simulating digital logic models. This document will describe the steps required to perform a behavioral simulation on a project or module. ModelSim® Tutorial, v10.5c 11 Chapter 2 Conceptual Overview ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog. This lesson provides a brief conceptual overview of the ModelSim simulation environment. It is divided into topics, which you will learn more about in subsequent lessons. EE 108 - Digital systems I Modelsim Tutorial Winter 2002-2003 Page 6 sur 14 In the next step you'll compile the Verilog design. The example design consists of two Verilog source files, each containing a unique module. The file counter.v contains a module called counter, which implements a simple 8-bit binary up-counter. Module Declaration A module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specifies the i/o type (input, output or inout, see Sect. 4.4. ) and width of each port. The default port width is 1 bit. The Python Tutorial If __all__ is not defined, If the imported module is not found in the current package (the package of which the current module is a submodule), the import statement looks for a top-level module with the given name. Xilinx ModelSim Simulation Tutorial CSE 372 (Spring 2006): Digital Systems Organization and Design Lab. ModelSim is a tool that integrates with Xilinx ISE to provide simulation and testing. Two kinds of simulation are used for testing a design: functional simulation and timing simulation. architectur