Describe what would have to change in the single cycle processor to implement t

1. Problem 5.2 Describe the effect that a single stuck-at- fault (i.e., regardless of what it should be, the signal is always 0) would have for the signals shown below, in the single-cycle datapath in Figure 5.17 on page 307. Which instructions, if any, will not work correctly? Explain why. a. RegWrite = 0 b. ALUop0 = 0 c. ALUop1 = 0 d. c. (3 pts) What is the clock cycle time and frequency of the multi-cycle processor? Also, what is the throughput assuming that instructions are equally distributed among store, load, and r-type instructions? d. (3 pts) How long does it take for an add, store, and load instruction to execute on a multi-cycle processor? e. (3 pts) For both single-cycle and multi-cycle processors, if you could Type 1: Given instruction set size and operands size and their count, find the size of the instruction. In this type of questions, you will be given the size of instruction set, number of operands and their size, you have to find out the size of the instruction. Que-1. Consider a processor with 64 registers and an instruction set of size twelve. The format of the instruction is as follows: beqr $s, $t, $d If the value of register s is equals to that of register t, we want to jump to the address specified as the value of register d. Give a proposal for adding such pseudo-instruction to the ISA (i.e., describe how it could be encoded in the I-Type, R-Type, or J-Type format. Instead of using a long list of Add instructions, it is possible to place a single Add instruction in a program loop, as shown below: Move N, R1 Clear R0 LOOP Determine address of "Next" number and add "Next" number to R0 Decrement R1 Branch > 0, LOOP Move R0, SUM Here is the assembly language form of the jump instruction. j target # after a delay of one machine cycle, # PC <-- address of target. 6 26 000010 00000000000000000000000000 -- fields of the instructuion opcode target -- meaning of the fields. There is room in the instruction for a 26-bit address. The 26-bit target address field is transformed Stage 1: Instruction Fetch Fetch a new instruction everycycle • Current PC is index to instruction memory • Increment the PC at end of cycle (assume no branches for now) Write values of interest to pipeline register (IF/ID) • Instruction bits (for later decoding) • PC+4 (for later computing branch targets) 24 IF PC instruction memory new pc addr mc HW6_w08_single-cycle-cpu_ch7.pdf - ECE366 Fall 2019 Homework 6 Problem 1 Textbook Exercise 7.1(a Suppose that the RegWrite control signal in the (c) jr (d) srl Data from problem 3 Modify the single-cycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure 7.11 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 7.8 to show the changes to the main decoder. Assembly - Logical Instructions. The processor instruction set provides the instructions AND, OR, XOR, TEST, and NOT Boolean logic, which tests, sets, and clears the bits according to the need of the program. The first operand in all the cases could be either in register or in memory. The second operand could be either in register/memory or an Exercise 7.3: